1. Field of the Invention
The present invention relates to a refresh control circuit and a method of controlling a refresh procedure of a semiconductor memory device, and more particularly to a refresh control circuit and a method of controlling a refresh procedure of the semiconductor memory device in which a refresh period is controlled according to temperature variation.
2. Description of the Related Art
A unit cell of a Dynamic Random Access Memory (DRAM) typically consists of one transistor and one storage capacitor to achieve a high degree of integration. An initial amount of electric charge in the storage capacitor may be reduced due to leakage current generated by the transistor. That is, data stored in the unit cell of the DRAM may be lost unintentionally. To prevent the loss of the data, a DRAM can perform a refresh operation. Specifically, the DRAM periodically reads the data stored in the unit cell and rewrites electronic charge corresponding to the read data to the storage capacitor. This operation is referred to as a refresh operation.
However, the DRAM may not perform either a read operation or a write operation when the DRAM is under a refresh operation mode. Therefore, an external device may not be able to access the DRAM during the refresh operation, which results in degradation in overall performance of the DRAM.
As the operating temperature of the DRAM increases, the period of time for which data in the storage capacitors of a DRAM cells are preserved decreases. Conversely, as the temperature of the DRAM decreases, the period of time for which data in the storage capacitor of the DRAM cell are preserved increases. Therefore, when the temperature of the DRAM cell increases, the DRAM needs to be refreshed more frequently to prevent a loss of the stored data.
However, in a conventional DRAM, the refresh period is determined according to the shortest data storing time. The shortest data storing time corresponds to when the DRAM is operating at its highest operating temperature of, for example, about 125° C. The refresh period determined in this manner is applied to the DRAM over its entire operating temperature range.
When the refresh operation occurs within the refresh period determined by the highest temperature that the DRAM can endure, the DRAM can unnecessarily perform frequent refresh operations when operating at a lower temperature. Such unnecessary refresh operations at the lower temperature may cause an increase in current consumption and lower the performance of the DRAM.